| 청구기호 |
TK7867-7867.5 |
| 판사항 |
1st ed. 2022.
|
| 형태사항 |
XII, 583 p. 215 illus., 211 illus. in color. online resource.
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| 언어 |
English |
| 내용 |
Introduction -- Analysis of Digital Design: Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning -- RouteNet: Routability Prediction for Mixed-size Designs Using Convolutional Neural Network -- High Performance Graph Convolutional networks with Applications in Testability Analysis -- MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification -- GRANNITE: Graph Neural Network Inference for Transferable Power Estimation -- Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes -- Optimization of Digital Design: Chip Placement with Deep Reinforcement learning -- DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement -- TreeNet: Deep Point Cloud Embedding for Routing Tree Construction -- Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing -- Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes -- PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning -- GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization -- Analysis and Optimization of Analog Design: Machine Learning Techniques in Analog Layout Automation -- Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks -- ParaGraph: Layout parasitics and device parameter prediction using graph neural network -- GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learn -- Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization -- Logic and Physical Verification: Deep Predictive Coverage Collection/ Dynamically Optimized Test Generation Using Machine Learning -- Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage -- Using Machine Learning Clustering To Find Large Coverage Holes -- GAN-OPC: Mask optimization with lithography-guided generative adversarial nets -- Layout hotspot detection with feature tensor generation and deep biased learning.
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| 주제 |
Electronic circuits.
Embedded computer systems.
Electronic circuit design.
Electronic Circuits and Systems.
Embedded Systems.
Electronics Design and Verification.
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| 보유판 및 특별호 저록 |
Springer Nature eBook
Printed edition: 9783031130731
Printed edition: 9783031130755
Printed edition: 9783031130762
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| ISBN |
9783031130748 |
| 기타 표준번호 |
10.1007/978-3-031-13074-8 |
| QR CODE |
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